Analogue Design For Teletubbies
Kevin Aylward B.Sc.
Power - Accuracy - Frequency Limit (PAFL) Of CMOS Amplifiers
Back to Contents
This paper addresses the theoretical limit of any CMOS amplifier with regards to the constraints of Power (current), Accuracy, and Frequency. Suitable modifications to the theory are easily made for bipolar amplifies, and are addressed in another paper.
Analogue design is always one of performance tradeoffs. One can rest assured that any tweak of a design that improves one aspect of its performance will always result in another aspect of its performance being inferior. It would therefor seem, that it should be possible to identify some key performance features, and construct some design equations that expressed such design limitations. This paper shows that for a given CMOS process, there is an inherent limit that links together, power (current), accuracy (untrimmed) and speed (gain bandwidth), thereby making it much clearer as to how to more optimally effect such design compromises in practice.
The initial motivation for this paper was based largely on the realization that principles behind the Heisenburg uncertainty relation regarding time and energy might be applied to electronic design. Clearly, it was not anticipated that the quantum mechanical limit itself would impact a typical analogue design, and that is indeed the case. However, its analysis certainly highlights some of the fundamental issues involved.
As a starter then, the Heisenburg time-energy relation is given by:
where ΔE is the rms uncertainty in energy and Δt is the time that the system (energy) remains in a given state. Given that the energy state is changing with time, this energy must be measured within this time period.
With a little hand waving (appendix C), the following relation can be derived:
The details of this result are not overly important, the key point being that this indicates that there is a minimum power for a signal or device, subject to a constraint of accuracy and speed of operation. Plugging in some numbers gives us nW's of power for GHz, 20bit signals, so the quantum limit is obviously no practical limit in terms of real designs. However, it does illustrate the basic connection between power, speed and accuracy. That is, there is always a relation of the form:
PAFL Power - Accuracy - Frequency Limit
It is first noted, that this derivation relies on suitable approximations that are usually reasonable valid in most situations. The purpose of the derivation is to formulate a reasonable "best case" such that the real circuit will generally always be worst. This allows an immediate determination of whether a given specification is achievable from the outset.
In appendix A, it is shown that, given a Width and Length of a mosfet, a relation can be formed relating the area of a mosfet to how accurately it matches another mosfet. This relation is:
where σ is the relative error and α is a constant.
This should be quite an intuitive equation. It simply says that the matching error is inversely proportional to the square root of the total area of the mosfet. Typically, manufactures characterize their process and empirically determine the value for alpha. It can therefor be taken as a known constant, just as any other process characteristic.
The starting point for this is the well-known capacitor current equation:
This equation represents an output voltage swinging across a capacitor load. If one considers a mosfet single transistor amplifier driven by a pure voltage source, the main capacitance across the transistors output is the gate drain capacitance and the drain bulk/substrate capacitance. The gate source capacitance will usually have negligible effect, assuming low gate resistance, with this type of voltage drive. The drain source capacitance can usually be ignored as well. It might be argued that a cascode connection might be faster, however, it should be noted that cascodes generally only offer an advantage when there is significant resistance in the gate drive that results in significant Miller roll off.
There are a two principal drain gate capacitances. One is proportional to Width X Length, but in the normal, active constant current saturation region, this one is negligible. The second capacitance is the overlap capacitance, and is proportional to the of the W of the device, so that C in (2) above can be expressed as:
where Cgdf, Cgbf are the respective specific capacitance's of the gate and drain bulk/substrate per unit length respectively.
Substituting (3) into (2)
Squaring (1) and Substituting into (4)
In appendix B it is shown that the small signal output current from a mosfet amplifier, when biased with a current I, is given by:
where K is a process constant and Vi is the small signal input voltage.
Since this current is the current that charges the load current, equations (5) and (6) can be equated to each other:
Thus, it can be seen that the minimum operating current of a mosfet amplifier depends on the square of the product of the amplifier's gain-bandwidth and accuracy, and with the process other fixed characteristics.
If the transistor operates in the linear region such that Cgd becomes a strong function of W X L, such that Cgd=WL.Cp, than the equation becomes:
Derivation of :
It is well known that a reasonable accurate large signal design equation for mosfets in the saturation region is given by:
This appendix does the hand waving argument on the quantum limit of power accuracy and frequency from:
The uncertainty in energy can be expressed by:
Where E is the energy being measured, or equivalently the energy being produced. Note that
This energy can be related to the power via:
Last updated 20th September 2009
Copyright © Kevin Aylward 1997-2009.
This paper may be reproduced so long as no charge is made,
and that the paper is reproduced in full, with full credit to it author given.