EDN Level Shifter

June 16^th 2014

The following is an examination of a design idea published online in EDN on 16^th June, 2014

The design idea was simulated in SuperSpice as an example showing some aspects of how to correctly perform an Analog design in simulation, for the real world.

Schematic

The design idea article presented as new, the topology on the right, identified as the Zener topology.

For the Zener topology, the article alleged that it was superior in comparison to an alleged “standard” topology. This “standard topology, is in fact non standard, and is shown on the left as the “Non standard” topology.

The actual “standard” or conventional topology is the topology in the middle notated as “Standard”. It has the advantage over the non standard topology because, for the same drive current, it is able to have a much lower resistance across the base emitter of the PNP, giving it a much faster response.

Nominal Simulated Output Waveforms

Output waveforms, at different High voltages, nominal models

VPS = 4.5V, 5V, 5.5V

Frequency = 500 kHz

Orange – Actual standard level shifter topology

Red – EDN Alleged standard level shifter topology (non standard)

Green – EDN Zener level shifter topology

Observations:

EDN Non standard topology fails, as claimed in the EDN article

EDN Zener topology fails even at nominal supply voltage. In contradiction to the claim in the EDN article.

Standard topology functions correctly.

Worst Case Corner Simulations

Weak and strong transistor models (hfe max, min)

Max and Min Zener voltage, +/-5%

Max and Min supply voltage +/-10%

All resisters nominal (to minimise number of graph traces)

High and low temperatures (-20c, +85c)

Observations:

Output of the Zener topology even more restricted over WC.

Output of the (actual) standard topology is correctly functional.

Conclusions

There is usually always a reason why certain obvious/simple circuits are not seen much in practice. Reinventing the already rejected square wheel is not a good idea.

Designs must account for all reasonable variations in operating conditions, and device parameters. e.g. Temperature, power supply voltages, min and max current gain of transistors etc.

Check the spice models and simulator. e.g. confirm that the data sheet minimum and maximum hfe spec is actually correct in the models and actually simulated.

Appendix

An alternate topology with the same parts count as the zener topology, and essentially the same performance as the standard topology is shown here:

Alternate Schematic

This topology also has the advantage that the current from the driving source is much lower, typically, lower than 200ua. Speed is now completely dominated by the PNP charge storage as the NPN is never in saturation, even at a high input drive of 3.63V.

Alternate Waveforms